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rev. pra 07/03 preliminary technical data preliminary technical data information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adf4360-2 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2003 integrated synthesizer and vco adf4360-2 functional block diagram features output frequency range: 1800 mhz to 2150 mhz divide-by-2 output +3.0 v to +3.6v power supply 1.8 v logic compatibility integer-n synthesizer programmable dual modulus prescaler 8/9, 16/17, 32/33 programmable output power level 3-wire serial interface analog and digital lock detect hardware and software power down mode applications wireless handsets (dect, gsm, pcs, dcs, wcdma) test equipment wireless lans catv equipment general description the adf4360-2 is a fully integrated integer-n synthesizer and voltage controlled oscillator (vco). the adf4360-2 is designed for a center frequency of 2000mhz. in addition, there is a divide-by-2 option available, whereby the user gets an rf output of between 900mhz and 1075mhz. control of all the on-chip registers is via a simple 3-wire interface. the device operates with a power supply rang- ing from 3.0v to 3.6v and can be powered down when not in use. prescaler p/p+1 13-bit b counter + - 5-bit a counter load load n = (bp + a) charge pump lock detect ref in 14-bit r counter clk data le 24-bit data register 24-bit function latch phase comparator adf4360-2 cp av dd dv dd ce agnd dgnd cpgnd r set v tune rf out a integer register vco core 2 c c c n multiplexer muxout rf out b v vco output stage multiplexer divsel = 1 divsel = 2
rev. pra 07/03 preliminary technical data ?2? parameter units test conditions/comments refin characteristics refin input frequency 10/250 mhz min/max for f < 10mhz, use dc-coupled cmos compatible square wave refin input sensitivity -3/0 dbm m in/max ac coupled. 0 to av dd volts max (cmos compatible) refin input capacitance 5.0 pf max refin input current 100 a max phase detector phase detector frequency 2 8 mhz max charge pump i cp sink/source 3 with r set = 4.7k ? . . . ? . . v cp 2.5 i cp vs. v cp 1.5 % typ 1.25v v cp 2.5 i cp vs. temperature 2 % typ v cp = 2.0v logic inputs v inh , input high voltage 1.5 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 3.0 pf max logic outputs v oh , output high voltage dv dd -0.4 v min cmos output chosen i oh 500 a max v ol , output low voltage 0.4 v max i ol = 500a power supplies av dd 3.0/3.6 v min/v max dv dd av dd vvco av dd ai dd 4 10 ma typ di dd 4 2.5 ma typ i vco 4,5 24.0 ma typ i core = 15ma. i rfout 4 3.5-11.0 ma typ rf output stage is programmeable low power sleep mode 7 a typ rf output characteristics 5 vco output frequency 1800/2150 m hz min/max i core = 15ma. vco sensitivity 57 mhz/volt lock time 400 us typ to within 10hz of final frequency. frequency pushing, (open loop) tbd mh z/volt typ frequency pulling, (open loop) tbd khz typ into 2.00 vswr load harmonic content (2nd) -20 dbc typ (3rd) -35 dbc typ output power 5,7 -13/-6 dbm typ programmable in 3db steps.table 3. output power variation +/- 3 db typ for tuned loads see page 18. vco tuning range 1.25/2.5 v min/max notes 1. operating temperature range is as follows: b version: ?40c to +85c. 2. guaranteed by design. sample tested to ensure compliance. 3. i cp is internally modified to maintain constant loop gain over the frequency range. 4. t a = +25c; av dd = dv dd = v vco = 3.3v; p = 32. 5. these characteristics are guaranteed for vco core power = 15ma. 6. jumping from 1.8ghz to 2.15ghz. pfd frequency = 200khz, loop bandwidth = 10khz. 7. using 50ohm resistors to vvco, into a 50ohm load. for tuned loads see page 18. adf4360 -2 specifications 1 (av dd = dv dd = v vco = +3.3v 10%; agnd = dgnd = 0 v; t a = t min to t max unless otherwise noted)
rev. pra 07/03 preliminary technical data ?3? adf4360 -2 specifications 1 (av dd = dv dd = v vco = +3.3v 10%; agnd = dgnd = 0 v; t a = t min to t max unless otherwise noted) parameter typ ical units test conditions/comments noise characteristics vco phase noise performance 2 -110 dbc/hz @ 100khz offset from carrier -130 dbc/hz @ 1mhz offset from carrier -141 dbc/hz @ 3mhz offset from carrier synthesizer phase noise floor 3 -172 dbc/hz @ 25khz pfd frequency -163 dbc/hz @ 200khz pfd frequency -147 dbc/hz @ 8mhz pfd frequency inband phase noise 4,5 -83 dbc/hz @ 1khz offset from carrier rms integrated phase error 6 0.64 degrees (100hz-100khz) spurious signals due to pfd frequency 5,7 -70 dbc notes 1. operating temperature range is as follows: ?40c to +85c. all measurements on this page for core power = 15ma. 2. the noise of the vco is meaured in open-loop conditions. 3. the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20logn (where n is the n divider value). 4. the phase noise is measured with the eval-adf4360-xeb1 evaluation board and the hp8562e spectrum analyzer. the spectrum anal yzer provides the refin for the synthesizer, f refin = 10mhz; offset frequency = 1 khz. 5. f refin = 10 mhz; f pfd = 200 khz; n = 10000; loop b/w = 10khz. 6. f refin = 10 mhz; f pfd = 1 mhz; n = 2000; loop b/w = 25khz. 7. the spurious signals are measured with the eval-adf4360-xeb1 evaluation board and the hp8562e spectrum analyzer. the spectr um analyzer provides the refin for the synthesizer (f refout = 10mhz @ 0dbm). ordering guide model temperature range frequency range package option* adf4360-1bcp ?40c to +85c 2050-2450 mhz cp-24 adf4360-2bcp ?40c to +85c 1700-2200 mhz cp-24 adf4360-3bcp ?40c to +85c 1550-1950 mhz cp-24 adf4360-4bcp ?40c to +85c 1400-1800 mhz cp-24 adf4360-5bcp ?40c to +85c 1150-1400 mhz cp-24 adf4360-6bcp ?40c to +85c 1000-1250 mhz cp-24 ADF4360-7BCP ?40c to +85c set by external l cp-24 pin configuration top view
13 14 15 16 17 18 1 2 3 4 5 6 pin 1 identifier cp gnd rf out a rf out b a gnd muxou t cc r set d vdd

a vdd a gnd a gnd cn ref in a gnd

preliminary technical data rev. pra 07/03 adf4360-2 ?4? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adf4360 family features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device? timing characteristics limit at t min to t max parameter (b version) units test conditions/comments t 1 20 ns min le set up time t 2 10 ns min data to clock set up time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le set up time t 7 20 ns min le pulse width (av dd = dv dd = v vco = +3.3v 10%; agnd = dgnd = 0 v; 1.8v and 3v logic levels used; t a = t min to t max unless otherwise noted) figure 1. timing diagram absolute maximum ratings 1, 2 ( t a = +25c unless otherwise noted) av dd to gnd 3 ...................................?0.3 v to +3.9 v av dd to dv dd ...................................?0.3 v to +0.3 v v vco to gnd......................................?0.3 v to +3.9 v v vco to av dd ......................................?0.3 v to +0.3 v digital i/o voltage to gnd..........?0.3 v to v dd + 0.3 v analog i/o voltage to gnd..........?0.3 v to v dd + 0.3 v ref in , to gnd............................?0.3 v to v dd + 0.3 v operatingtemperature range maximum junction temperature........................+150c csp ....................................... ................................. ...................................... ............................................ . . . . . . . . t 6 t 7 clock db23 (msb) db22 db2 db1 (control bit c2) data le le db0 (lsb) (control bit c1) t 2 t 3 t 4 t 5 t 1
preliminary technical data rev. pra 07/03 ?5? adf4360-2 pin description mnemonic function av dd analog power supply. this may range from 3.0v to 3.6v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd. dv dd digital power supply. this may range from 3.0v to 3.6v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . v vco power supply for the vco. this may range from 3.0v to 3.6v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. v vco must be the same value as av dd. r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output current for the synthesizer. the nominal voltage potential at the r set pin is 0.6v. the relationship between i cp and r set is so, with r set = 4.7k ? .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?. . . i cpmax = r set 11.75
preliminary technical data rev. pra 07/03 ?6? adf4360-2 tpc 1. open loop vco phase noise tpc 2. vco phase noise, 2000mhz, 200khz pfd, 10khz loop bandwidth. tpc 4. close-in phase noise at 2000mhz (200khz channel spacing) typical performance characteristics: tpc 6 reference spurs at 2000mhz (1mhz channel spacing, 25khz loop bandwidth) tpc 5. reference spurs at 2000mhz (200khz channel spacing, 10khz loop bandwidth) 2000mhz +0.5mhz +1mhz -0.5mhz -1mhz res. bandwidth = 30khz video bandwidth = 30khz averages = 100 v dd = +3v, v vco = +3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 25khz sweep = 50 ms -10 output power (db's) -20 -30 -40 -50 -60 -70 -80 -90 0 -83.8dbc/hz 2000mhz +100khz +200khz -100khz -200khz res. bandwidth = 3khz video bandwidth = 3khz averages = 100 v dd = +3v, v vco = +3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz sweep = 140 ms -10 output power (db's) -20 -30 -40 -50 -60 -70 -80 -90 0 -79.5dbc 2000mhz +1khz +2khz -1khz -2khz res. bandwidth = 30hz video bandwidth = 30hz averages = 10 v dd = +3v, v vco = +3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz sweep = 1.9 seconds -10 output power (db's) -20 -30 -40 -50 -60 -70 -80 -90 0 -84.0dbc/hz ! "#$%&' ! ( ! "$) ! "$** ! "$# tpc 3. vco phase noise, 1000mhz, divide by 2 enabled 200khz pfd, 10khz loop bandwidth.
preliminary technical data adf4360-2 rev. pra 07/03 ?7? figure 2. reference input stage a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 300mhz or less. thus, with an vco frequency of 2.5ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. pulse swallow function the a and b counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by r . the equation for the vco frequency is as follows: f vco = [(p x b) + a] x f refin /r f vco ouput frequency of voltage controlled oscillator (vco). p preset modulus of dual modulus prescaler (8/9, 16/17, etc.,). b preset divide ratio of binary 13-bit counter (3 to 8191). a preset divide ratio of binary 5-bit swallow counter (0 to 31). f refin external reference frequency oscillator. powerdown control 100k ? . . . . . . . . . . . . .
preliminary technical data rev. pra 07/03 ?8? 0000?0?01/00 (rev. 0) 00000 printed in u.s.a. adf4360-2 r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter (n=bp+a) and produces an output proportional to the phase and frequency difference between them. figure 4 is a simplified schematic. the pfd includes a programmable delay element which controls the width of the anti-backlash pulse. this pulse ensures that there is no deadzone in the pfd transfer function and minimizes phase noise and reference spurs. two bits in the r counter latch, abp2 and abp1 control the width of the pulse. see page 14. figure 4. pfd simplified schematic and timing (in lock) figure 5. muxout circuit input shift register the adf4360 family?s digital section includes a 24-bit input shift register, a 14-bit r counter and a 18-bit n counter, comprising a 5-bit a counter and a 13-bit b counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsb's db1, db0 as shown in the timing diagram of figure 1. the truth table for these bits is shown in table 1. table 2 shows a summary of how the latches are programmed. please note that the test modes latch is used for factory testing snd should not be programmed by the user. control bits c2 c1 data latch 0 0 control latch 0 1 r counter 1 0 n counter (a & b) 1 1 test modes latch hi hi d1 d2 q1 q2 clr1 clr2 cp programmable delay u1 u2 u3 up down charge pump abp2 abp1 cpgnd v p r divider n divider r divider n divider cp output analog lock detect muxout control digital lock detect r counter output n counter output sdout mux dv dd dgnd table i. c2, c1 truth table muxout and lock detect the output multiplexer on the adf4360 family allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2 and m1 in the function latch. the full truth table is shown on page 13. figure 5 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when ldp in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15ns. with ldp set to "1", five consecutive cycles of less than 15ns phase error are required to set the lock detect. it will stay set high until a phase error of greater than 25ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10k ? . .
preliminary technical data adf4360-2 rev. pra 07/03 ?9? vco the vco core in the adf4360 family uses eight overlapping bands as shown in figure 6 to allow a wide frequency range to be covered without a large vco sensitivity (kv) and resultant poor phase noise and spurious performance. the correct band is chosen automatically by the band select logic at power-up or whenever the n counter latch is updated. it is important that the correct write sequence be followed at power-up. this sequence is: 1) r counter latch 2) control latch 3) n counter latch during band select, which takes five pfd cycles, the vco vtune is disconnected from the output of the loop filter and connected to an internal reference voltage. the operating current in the vco core is programmable in four steps, 5ma, 10ma, 15ma & 20ma. this is controlled by bits pc1 & pc2 in the control latch. output stage the rfouta and rfoutb pins of the adf4360 family are connected to the collectors of an npn differential pair driven by buffered outputs of the vco as shown in figure 7. to allow the user to optimise his/her power dissipation vs output power requirements, the tail current of the differential pair is programmable via bits pl1 & pl2 in the control latch. four current levels may be set; 3.5ma, 5ma, 7.5ma and 11ma giving output power levels of - 13dbm, -10.5dbm, -8dbm & -6dbm using a 50ohm resistor to vdd and ac-coupling into a 50ohm load. alternatively, both outputs can be combined in a 1+1:1 transformer or a 180 microstrip coupler. see page 19. if the outputs are to be used individually, then the optimum output stage consists of a shunt inductor to vdd. another feature of the adf4360 family is provided whereby the supply current to the rf output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. this is enabled by the mtld (mute till lock detect) bit in the control latch. figure 6 frequency vs vtune, adf4360-2 after band select, normal pll action resumes. the nominal value of kv is 57mhz/volt or 28mhz/volt if divide by two operation has been selected (by programming divsel (db22), high in the n counter latch). the adf4360 family contains linearisation circuitry to minimise any variation of the product of icp and kv. the r counter output is used as the clock for the band select logic and should not exceed 1mhz. a programmable divider is provided at the r counter input to allow division by 1,2,4 or 8, and is controlled by bits bsc1 and bsc2 in the r counter latch. where the required pfd frequency exceeds 1 mhz the divide ratio should be set to allow enough time for correct band selection. vco buffer / divide by 2 rf out a rf out b figure 7 rf output stage adf4360-2
preliminary technical data rev. pra 07/03 ?10? 0000?0?01/00 (rev. 0) 00000 printed in u.s.a. adf4360-2 table ii: latch structure the diagram below shows the three on-chip latches for the adf4360 family. the two lsb?s decide which latch is programmed. db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) cr pd1 m1 m2 m3 cp p1 p2 cpi1 cpi2 cpi5 cpi6 pd2 pdp control bits counter reset power down 1 muxout control phase detector polarity cp 3-state power down 2 current setting 1 prescaler value cpi3 cpi4 db21 current setting 2 db22 db23 cp gain cpg mtld output power level pl2 pl1 pc2 pc1 core power level mute till ld control latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv control bits 5-bit a counter 13-bit b counter db21 db22 db23 cp gain cpg divsel div2 reserved divide by 2 divide by 2 select n counter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp control bits 14-bit reference counter, r lock detect precision reserved db21 db22 db23 anti backlash width rsv rsv bsc2 bsc1 tmb r counter latch band select clock test mode bit
preliminary technical data adf4360-2 rev. pra 07/03 ?11? table iii: control latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 m2 m3 pdp p1 p2 cpi2 cpi3 cpi6 pd1 cpi1 pd2 control bits muxout control counter reset cp 3-state power down 2 current setting 1 prescaler value cpi4 cpi5 db21 current setting 2 pl2 pl1 mtld db22 db23 cp gain cp cpg p2 p1 prescaler value 0 0 8/9 0 1 16/17 1 0 32/33 1 1 32/33 ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 1 0 1 asynchronous power-down 1 1 1 synchronous power-down cpi6 cpi5 cp14 i cp (ma) cpi3 cpi2 cpi1 4.7k ? . . . . . . . . . . . . . .
preliminary technical data rev. pra 07/03 ?12? 0000?0?01/00 (rev. 0) 00000 printed in u.s.a. adf4360-2 table iv: r counter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 ldp control bits 14-bit reference counter lock detect precision reserved db21 db22 db23 x bsc2 anti backlash width ldp lock detect precision 0 3 consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1 5 consecutive cycles of phase delay less than 15ns must occur before lock detect is set. test mode bit should be set to 0 for normal operation abp2 abp1 anti-backlash pulse width 0 0 3.0ns 0 1 1.3ns 1 0 6.0ns 1 1 3.0ns r14 r13 r12 .......... r3 r2 r1 divide ratio 0 0 0 .......... 0011 0 0 0 .......... 0102 0 0 0 .......... 0113 0 0 0 .......... 1004 . . . .......... .... . . . .......... .... . . . .......... .... 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 x x = don?t care reserved test mode bit bsc1 band select clock these bits are not used by the device and are don't care bits. bsc2 bsc1 band select clock divider 001 012 104 118
preliminary technical data adf4360-2 rev. pra 07/03 ?13? table v: n counter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv control bits 5-bit a counter 13-bit b counter db21 reserved db22 db23 cp gain cpg these bits are not used by the device and are don't care bits. f4 (function latch) cp gain operation fastlock enable 0 0 charge pump current setting 1 is permanently used 0 1 charge pump current setting 2 is permanently used b13 b12 b11 b3 b2 b1 b counter divide ratio 0 0 0 .......... 000not allowed 0 0 0 .......... 001not allowed 0 0 0 .......... 010not allowed 0 0 0 .......... 1113 . . . .......... .... . . . .......... .... . . . .......... .... 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 a5 a4 .......... a2 a1 a counter divide ratio 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 28 1 1 .......... 0 1 29 1 1 .......... 1 0 30 1 1 .......... 1 1 31 n = bp + a, p is prescaler value set in the control latch. b must be greater than or equal to a. for continuously adjacent values of (n x f ref ), at the output, n min is (p 2 - p) xx x = don?t care these bits are not used by the device and are don't care bits. reserved
preliminary technical data rev. pra 07/03 ?14? 0000?0?01/00 (rev. 0) 00000 printed in u.s.a. adf4360-2 control latch with (c2, c1) = (0,0), the control latch is programmed. table iii shows the input data format for programming the control latch. prescaler value in the adf4360 family, p2 and p1 in the control latch set the prescaler values. power-down db21 (pd2) and db20 (pd1) provide programmable power- down modes. in the programmed asynchronous power-down, the device powers down immediately after latching a ?1? into bit pd1, with the condition that pd2 has been loaded with a ?0?. in the programmed synchronous power-down, the device power down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a ?1? into bit pd1 (on condition that a ?1? has also been loaded to pd2), then the device will go into power-down on the second rising edge of the r counter output, after le goes high. when the ce pin is low, the device is immediately disabled regardless of the states of pd1 or pd2. when a power down is activated (either synchronous or asynchronous mode), the following events occur: all active dc current paths are removed. the r, n and timeout counters are forced to their load state conditions. the charge pump is forced into three-state mode. the digital lock detect circuitry is reset. the rf outputs are debiased to a high impedance state. the reference input buffer circuitry is disabled. the input register remains active and capable of loading and latching data. charge pump currents cpi3, cpi2, cpi1 in the adf4360 family determine current setting 1. cpi6, cpi5, cpi4 determine current setting 2. the truth table is given in table iii. output power level bits pl1 & pl2 set the output power level of the vco. the truth table is given in table iii. mute till lock detect db11 of the control latch in the adf4360 family is the mute till lock detect bit. this function, when enabled, ensures that the rf outputs are not switched on until the pll has achieved lock. cp gain bit db10 of the control latch in the adf4360 family is the charge pump gain bit. when this is programmed to a ?1? then current setting 2 is used. when programmed to a ?0?, current setting 1 is used. charge pump three-state this bit puts the charge pump into three-state mode when programmed to a ?1?. it should be set to ?0? for normal operation. phase detector polarity the pdp bit in the adf4360 family sets the phase detector polarity. the positive setting enabled by programming a ?1? is used when using the on-chip vco with a passive loop filter or with an active non-inverting filter. it can also be set to ?0?. this is required if an active inverting loop filter is used. muxout control the on-chip multiplexer is controlled by m3, m2, m1. table 3 shows the truth table. counter reset db4 is the counter reset bit for the adf4360 family. when this is ?1?, the r counter and the a,b counters are reset. for normal operation this bit should be ?0?. core power level pc1 and pc2 set the power level in the vco core. the recommended setting is 15ma. the truth table is given in table iii.
preliminary technical data adf4360-2 rev. pra 07/03 ?15? n counter latch with (c2, c1) = (1,0), the n counters latch is programmed. a counter latch a5 - a1 program the 5-bit a counter. the divide range is 0 (00000) to 31 (11111). reserved bits db7 is a spare bit and has been designated as ?reserved?. it should be programmed to ?0?. b counter latch b13 - b1 program the b counter. the divide range here is 3 (00.....0011) to 8191 (11....111). overall divide range the overall divide range is defined by ((pxb) + a), where p is the prescaler value. cp gain bit db21 of the n counter latch in the adf4360 family is the charge pump gain bit. when this is programmed to a ?1? then current setting 2 is used. when programmed to a ?0?, current setting 1 is used. this bit can also be programmed via db10 of the control latch. the bit will always reflect the latest value written to it, whether this is through the control latch or the n counter latch. divide by 2 db22 is the divide-by-2 bit. when set to a ?1?, the output divide by 2 function is chosen. when it is set to ?0?, normal operation occurs. divide by 2 select db23 is the divide-by-2 select bit. when this is programmed to a ?1?, the divide-by-2 output is selected as the prescaler input. when it is set to a ?0?, the fundamental is used as the prescaler input. for example: using the output divide by two feature, and a pfd frequency of 200khz the user will need a value of n = 10000 to generate 1ghz. with the divide by two select bit high, the user may keep n = 5000. r counter r1 to r14 sets the counter divide ratio. the divide range is 1 (00.....001) to 16383 (111......111). anti-backlash pulse width db16 and db17 set the anti-backlash pulse width. lock detect precision bit db18 is the lock detect precision bit and sets the number of references cycles with less than 15ns phase error for entering the locked state. with ldp at ?1?, 5 cycles are taken and with ldp at ?0?, 3 cycles are taken. test mode bit. db19 is the test mode bit (tmb) and should be set to zero. with tmb = 0, the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch, r counter latch, and n counter latch. please note that test modes are for factory testing only, and should not be programmed by the user. band select clock bits these bits set a divider for the band select logic clock input, the output of the r counter is by default the value used to clock the band select logic, but if this value is too high (>1mhz), a divider can be switched in to divide the r counter output to a smaller value. see table 4. reserved bits db23 - db22 are spare bits and have been designated as ?reserved?. they should be programmed to ?0?. r counter latch with (c2, c1) = (0,1), the r counter latch is programmed.
preliminary technical data rev. pra 07/03 ?16? 0000?0?01/00 (rev. 0) 00000 printed in u.s.a. adf4360-2 applications section direct conversion modulator direct conversion architectures are being increasingly used to implement base station transmitters. figure 7 shows how adi parts can be used to implement such a system. the circuit block diagram shows the ad9761 txdac being used with the ad8349. the use of dual integrated dac?s such as the the ad9761 with specified 0.02db and 0.004db gain and offset matching characteristics ensures minimum error contribution (over temperature) from this portion of the signal chain. the local oscillator is implemented using the adf4360-2. the low-pass filter was designed using adisimpll, for a channel spacing of 100khz and an open-loop bandwidth chosen of 10khz. the frequency range of the adf4360-2 (1.8-2.15ghz) makes it ideally suited for implementation of a w-cdma transceiver. the lo ports of the ad8349 can be driven differentially from the complementary rfouta and rfoutb outputs of the adf4360-2. this gives a better performance than a single- ended lo driver, and eliminates the often necessary use of a balun to convert from a single-ended lo input to the more desireable differential lo inputs for the ad8349. the typical rms phase noise (100hz-100khz) of the lo in this configuration is 2.1 degrees. the ad8349 accepts lo drive levels from -10 to 0dbm. the optimum lo power can be software programmed on the adf4360-2, which allows levels from -12 to -3 dbm from each output. the rf output is designed to drive a 50 ? . . . ? ? ? ?
preliminary technical data adf4360-2 rev. pra 07/03 ?17? fixed frequency lo: the following diagram shows the adf4360-2 used as a fixed frequency lo at 2.0ghz. the low-pass filter was designed using adisimpll, for a channel spacing of 8mhz and an open-loop bandwidth of 45khz. 8mhz is the maximum pfd frequency of the adf4360-2. since using a larger pfd frequency allows us to use a smaller n. the in-band phase noise is reduced to as low as possible, -99dbc/hz. the 40khz bandwidth is chosen to be just greater than the point at which open-loop phase-noise of the vco is -99dbc/hz, thus giving the best possible integrated noise. the typical rms phase noise (100hz-100khz) of the lo in this configuration is 0.3 degrees. the reference frequency is from a 16mhz tcxo from fox. thus an r value of 2 is programmed. taking account of the high pfd frequency, and the effect this has on the band select logic, the band select clock divider is enabled. in this case a value of 8 is chosen. a very simple pull-up resistor and dc blocking capacitor complete the rf output stage. figure 9. single frequency lo. &* $& ? ? ?? ? ? ? ?
preliminary technical data rev. pra 07/03 ?18? 0000?0?01/00 (rev. 0) 00000 printed in u.s.a. adf4360-2 interfacing the adf4360 family has a simple spi-compatible serial interface for writing to the device. clk , data and le control the data transfer. when le goes high the 24 bits which have been clocked into the appropriate register on each rising edge of clk will get transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20mhz. this means the maximum update rate possible is 833khz or one update every 1.2 microseconds. this is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. aduc812 interface figure 9 shows the interface between the adf4360 family and the aduc812 microconverter. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is setup for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4360 family is needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written the le input should be brought high to complete the transfer. power up. after power-up, the part needs a three writes for normal operation. the correct sequence is to the r counter latch, followed by the control latch and finally the n counter latch. adsp-2181 interface figure 10 shows the interface between the adf4360 family and the adsp-21xx digital signal processor. the adf4360 family needs a 24-bit serial word for each latch write. the easiest way to accomplish this is using the adsp -21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the 8-bit bytes, enable the autobuffered mode and then write to the the transmit register of the dsp. this last operation initiates the autobuffer transfer. pcb design guidelines for chip scale package the lands on the chip scale package (cp-24) are rectangular. the printed circuit board pad for these should be 0.1mm longer then the package land length and 0.05mm wider than the package land width. the land should be centered on the pad. this will ensure that the solder joint size is maximised. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed curcuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this will ensure that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2mm pitch grid. the via diameter should be between 0.3mm and 0.33mm and the via barrel should be plated with 1oz copper to plug the via. the user should connect the printed circuit thermal pad to agnd. this is internally connected to agnd. adsp21xx adf4360-x sclk sdata le ce muxout (lock detect) sclk dt i/o flags { tfs aduc812 adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi i/o ports { figure 10. aduc812 to adf4360-x interface figure 11. adsp-21xx to adf4360-x interface i/o port lines on the aduc812 are also used to control powerdown (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4mhz. this means that the maximum rate at which the output frequency can be changed is 166khz.
preliminary technical data adf4360-2 rev. pra 07/03 ?19? output matching there are a number of ways to match the output of the adf4360-2 for optimum operation. the most basic of these is to use a 50ohm resistor to vvco. a dc bypass capacitor of 100pf is connected in series as shown below. because the resistor is not frequency dependent, this provides a good broadband match. the output power in a circuit below gives typically -6dbm output power into a 50ohm load. a better solution is to use a shunt inductor (acting as an rf choke) to vvco, this gives a better match and hence more output power, additionally a series inductor is added after the dc bypass capacitor to provide a resonant lc circuit. this tunes the oscillator output and provides approximately 10db further rejection of the 2nd harmonic. the shunt inductor needs to be a relatively high value (>40nh). experiments have shown that the following circuit provides an excellent match to 50ohms over the operating range of the adf4360-2. this gives approximately -2dbm output power across the frequency range of the adf4360-2. both single- ended architectures can be examined using the eval_adf4360-2eb1 evaluation board. " $ ? ? . . . . . . . . . . . . . . . . . ? ?
preliminary technical data rev. pra 07/03 ?20? 0000?0?01/00 (rev. 0) 00000 printed in u.s.a. adf4360-2 1 24 6 7 13 19 18 bottom view 12 0.080 (2.25) 0.083 (2.10) sq 0.077 (1.95) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.098 (2.50) ref 0.010 (0.25) min 0.020 (0.50) bsc 12 o max 0.008 (0.20) ref 0.028 (0.70) max 0.026 (0.65) nom 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) 0.035 (0.90) max 0.033 (0.85) nom seating plane controlling dimensions are in millimeters pin 1 indicator top view 0.148 (3.75) bsc sq 0.157 (4.0) bsc sq outline dimensions dimensions shown in inches and (mm)

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